It goes without saying that designing complex semiconductors is an extremely challenging engineering process. While the chips themselves are small, and the individual features on the chips are tiny, as small as 7 nanometers (seven billionths of a meter), the intricacy of the design process is astronomical.
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Table Of Contents:
- Introduction
- The Challenges Of Optimizing The Broader Design Space
- The Evolution of ML in Electronic Design
- The Path Forward For AI In Chip Design
- Conclusions And Recommendations
- Figure 1: Traditional Physical Design Space Exploration
- Figure 2: Machine Learning In Physical Design
- Figure 3: The Synopsys DSO.ai Design Space Optimization System
- Figure 4: Synopsys DSO.ai Customer Results
Companies Cited:
- Synopsys
Patrick founded the firm based on his real-world world technology experiences with the understanding of what he wasn’t getting from analysts and consultants. Ten years later, Patrick is ranked #1 among technology industry analysts in terms of “power” (ARInsights) in “press citations” (Apollo Research). Moorhead is a contributor at Forbes and frequently appears on CNBC. He is a broad-based analyst covering a wide variety of topics including the cloud, enterprise SaaS, collaboration, client computing, and semiconductors. He has 30 years of experience including 15 years of executive experience at high tech companies (NCR, AT&T, Compaq, now HP, and AMD) leading strategy, product management, product marketing, and corporate marketing, including three industry board appointments.
